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关于SI4432双工通信收发冲突

ST游徒提问时间：2014-8-27 14:16 /

问答
是否解决:

在使用si4432时，单工可以很好实现，一个收另一个发，没有问题。现在要做双工通信，默认情况为接收状态，接收结果显示在串；串口触发SI4432发送。但是现在出现一个问题是：当发送的时候，在发送方串口会同时显示上次接受的数据的第一个数据并和上次接收数据个数一样。我一步一步调试发现两个中断位都响应了，但是我在发送后的中断函数最后默认了接收模式啊。。。。。。。。请大神给点指示，如何调试

赞收藏评论5 发布时间：2014-8-27 14:16

5个回答

霹雳之火回答时间：2014-8-27 14:50:23

RE:关于SI4432双工通信收发冲突

SI4432是款射频芯片吧，没用过，楼主最好把代码贴出来，让大神来看看

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ST游徒回答时间：2014-8-27 15:08:46

回复:关于SI4432双工通信收发冲突

回复第 2 楼于2014-08-27 14:50:23发表:
SI4432是款射频芯片吧，没用过，楼主最好把代码贴出来，让大神来看看

void Si4432_ISR(void)
{
uint8_t status1 = 0;
uint8_t status2 = 0;
uint8_t SI4432_RxLenth = 0;

statebuf[2] = SPI_Read(0x02);
delay_ms(1);
status1 = SPI_Read(0x03); //read the Interrupt Status1 register
status2 = SPI_Read(0x04); //read the Interrupt Status2 register, just for clear the pending bits?

statebuf[3] = SPI_Read(0x02);
if(status1==0x26)
{
    if(rx_flag ==1)
{
    status1 =0x24;
rx_flag ^=1;
}
}
   if ( (status1 & 0x02) == 0x02 ) /*Valid Packet Received*/
{
rx_flag |= 2;
SI4432_RxLenth = SPI_Read(0x4B);
for (SI4432_RxCount=0;SI4432_RxCount < SI4432_RxLenth;SI4432_RxCount++)
{
SI4432_RxBUFF[SI4432_RxCount] = SPI_Read(0x7F);
}

// SPI_RW_Reg(0x08, 0x02);
// SPI_RW_Reg(0x08, 0x00);
// SPI_RW_Reg(0x07, 0x05); //enble rx
statebuf[4] = SPI_Read(0x02);
}
if( (status1 & 0x04) == 0x04 ) /* packet sent interrupt*/
{
tx_ok = 1;
statebuf[5] = SPI_Read(0x02);
}

statebuf[6] = SPI_Read(0x02);
SPI_RW_Reg(0x08, 0x03);
SPI_RW_Reg(0x08, 0x00);

SPI_RW_Reg(0x07,0x01);
delay_ms(10);

SPI_RW_Reg(0x05, 0x03); /* enable rx interrupt*/
SPI_RW_Reg(0x06, 0x00);
SPI_RW_Reg(0x07, 0x05); //enble rx
status1 = SPI_Read(0x03); //read the Interrupt Status1 register
status2 = SPI_Read(0x04); //read the Interrupt Status2 register, just for clear the pending bits?

statebuf[7] = SPI_Read(0x02);
}

void Si4432Send(uint8_t* buf, uint8_t len)
{
if(tx_ok)
{
SI4432_RxBUFF[rx_count++] = SPI_Read(0x5);
SI4432_RxBUFF[rx_count++] = SPI_Read(0x6);
SI4432_RxBUFF[rx_count++] = SPI_Read(0x7);
SI4432_RxBUFF[rx_count++] = SPI_Read(0x8);

SPI_RW_Reg(0x07, 0x01); //ready mode
delay_ms(10); // delay for stable

SPI_RW_Reg(0x3e, len); // SET transimit length
while(len--)
SPI_RW_Reg(0x7F, *buf++);

statebuf[9] = SPI_Read(0x02);
SPI_RW_Reg(0x05, 0x04); //enable trasimition complete interrupt
SPI_RW_Reg(0x06, 0x00);
SPI_Read(0x03); //clear interrupt flags
SPI_Read(0x04);
SPI_RW_Reg(0x07, 0x09); // transmition enable

statebuf[10] = SPI_Read(0x02);
tx_ok = 0;
}
}

int main(void)
{
RCC_Configuration();
GPIO_Configuration();
NVIC_Configuration();
USART2_Configuration();
JrInit();
// printf("wholly shit");
uprintf("si4432 poc");
/*software reset*/
SPI_RW_Reg(0x07, 0x80);
delay_ms(100);
// while(GPIO_ReadInputDataBit(TIP_JR_IRQ_PORT,TIP_JR_IRQ_PIN) == SET);
SI4432_RxBUFF[rx_count++] = SPI_Read(0x3);
SI4432_RxBUFF[rx_count++] = SPI_Read(0x4);
SI4432_RxBUFF[rx_count++] = SPI_Read(0x5);
SI4432_RxBUFF[rx_count++] = SPI_Read(0x6);
delay_ms(100);

SPI_RW_Reg(0x75, 0x53);
SPI_RW_Reg(0x76, 0x64); //
SPI_RW_Reg(0x77, 0x00);

SI4432_RxBUFF[rx_count++] = SPI_Read(0x75);
SI4432_RxBUFF[rx_count++] = SPI_Read(0x76);
SI4432_RxBUFF[rx_count++] = SPI_Read(0x77);

SPI_RW_Reg(0x2a, 0x14);
SPI_RW_Reg(0x6e, 0x09);
SPI_RW_Reg(0x6f, 0xd5);
SPI_RW_Reg(0x70, 0x2c);

//SpiWriteRegister(0x72, 0x48); //(9.6kbps)
SPI_RW_Reg(0x72, 0x38); // frequency bias (1.2kbps)
//(9.6 kbps, deviation: 45 kHz, channel filter BW: 102.2 kHz
SPI_RW_Reg(0x1C, 0x1b); //write 0x1E to the IF Filter Bandwidth register
SPI_RW_Reg(0x20, 0x83); //write 0xD0 to the Clock Recovery Oversampling Ratio register
SPI_RW_Reg(0x21, 0xc0); //write 0x00 to the Clock Recovery Offset 2 register
SPI_RW_Reg(0x22, 0x13); //write 0x9D to the Clock Recovery Offset 1 register
SPI_RW_Reg(0x23, 0xa9); //write 0x49 to the Clock Recovery Offset 0 register
SPI_RW_Reg(0x24, 0x00); //write 0x00 to the Clock Recovery Timing Loop Gain 1 register
SPI_RW_Reg(0x25, 0x03); //write 0x24 to the Clock Recovery Timing Loop Gain 0 register
SPI_RW_Reg(0x1D, 0x40); //write 0x40 to the AFC Loop Gearshift Override register
SPI_RW_Reg(0x1E, 0x0A); //write 0x0A to the AFC Timing Control register
SPI_RW_Reg(0x2A, 0x14); //write 0x20 to the AFC Limiter register

/* preamble & synchronous words configuration*/
SPI_RW_Reg(0x34, 0X0A); // 5 bytes of preamble
SPI_RW_Reg(0x35, 0x2A); // preamble check enable
SPI_RW_Reg(0x33, 0x02); // Transmitted Synchronization Word 3 first, followed by sync word 2
SPI_RW_Reg(0x36, 0x2d); //Synchronization Word 0x2dd4
SPI_RW_Reg(0x37, 0xd4);
SPI_RW_Reg(0x30, 0x8D); //enalbe PH+FIFO MODE, MSB, CCITT CRC
SPI_RW_Reg(0x32, 0x00 ); // disable frame header
SPI_RW_Reg(0x71, 0x63); // tranismit without CLK, FIFO, FSK MODE

/*GPIO configuration*/
SPI_RW_Reg(0x0b, 0x12); //
SPI_RW_Reg(0x0c, 0x15); //

/* others configuration */
SPI_RW_Reg(0x09, 0xD7); // loading capacity
SPI_RW_Reg(0x69, 0x60); //AGC overload

/* tx power*/
SPI_RW_Reg(0x6d, 0x1e);

/* enable rx manually*/
SPI_RW_Reg(0x07, 0x05);

/* enable rx interrupt*/
SPI_RW_Reg(0x05, 0x03);
SPI_RW_Reg(0x06, 0x00);

/* clear interrupt*/
SI4432_RxBUFF[rx_count++] = SPI_Read(0x03);
SI4432_RxBUFF[rx_count++] = SPI_Read(0x04);

statebuf[0] = SPI_Read(0x02);

for(;;)
{
if(rx_flag & 1)
{
//rx_flag ^= 1;
delay_ms(2);
Si4432Send(uart_rx_buf, uart_rx_count);
uart_rx_count = 0;
   statebuf[14] = SPI_Read(0x02);
}
if(rx_flag & 2)
{
rx_flag ^= 2;
delay_ms(2);
unprint((char*)SI4432_RxBUFF, SI4432_RxCount);
SI4432_RxCount=0;

statebuf[15] = SPI_Read(0x02);
}
delay_ms(5);
}
}

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