Core
32-bit ARM® Cortex®-M7 core with double-precision FPU and L1 cache: 16 KB of data and 16 KB of instruction cache allowing to fill one cache line in a single access from the 256-bit embedded Flash memory; frequency up to 400 MHz, MPU, 856 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
Memories
Up to 2 MB of Flash memory with read while write support
~1 MB of RAM: 192 KB of TCM RAM (inc. 64 KB of ITCM RAM + 128 KB of DTCM RAM for time critical routines), 864 KB of user SRAM, and 4 KB of SRAM in Backup domain
Dual mode Quad-SPI memory interface
Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
CRC calculation unit
Security
ROP, PC-ROP, active tamper
Reset and power management
3 separate power domains which can be independently set in low-power mode to maximize power efficiency (clock gated or switched off)1: high-performance capabilities for high bandwidth peripheralsD2: dedicated to communication peripherals and timersD3: reset and clock control, plus power management
1.62 to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
Voltage scaling in Run and Stop mode
Backup regulator (~0.9 V)
Voltage reference for analog peripheral and VREF+
Low-power modes: Sleep, Stop and Standby
Low-power consumption
Total current consumption down to 7 μA
Clock management
Internal oscillators: 64 MHz HSI oscillator, 48 MHz RC oscillator, 4 MHz CSI oscillator, 40 kHz LSI oscillator
External oscillators: 1-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
3x PLLs (1 for the system clock, 2 for kernel clocks) with fractional mode
General-purpose input/outputs
Up to 168 I/O ports with interrupt capabilityUp to 4 fast I/Os up to 166 MHzUp to 89 I/Os up to 83 MHzUp to 164 5 V-tolerant I/Os
Interconnect matrix
4 DMA controllers to unload the CPU
Up to 35 communication peripherals
4× I2C FM+ interfaces (SMBus/PMBus)
4× USART/4x UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1× LPUART
6× SPIs, including 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock and 1x I2S in LP domain
4× SAIs (serial audio interface)
SPDIFRX interface
SWPMI single-wire protocol master I/F
MDIO Slave interface
2× SD/SDIO/MMC interfaces
2× CAN controllers supporting CAN FD protocol, out of which one supports time-triggered CAN (TT-CAN)
2× USB OTG interfaces (1FS, 1HS/FS)
Ethernet MAC interface with DMA controller
HDMI-CEC
8- to 14-bit camera interface up to 80 MHz
11 analog peripherals
3× ADCs with 16-bit max. resolution (14 bits 2.7 MSPS, 16 bits 168 kSPS)
1× temperature sensor
2× 12-bit D/A converters (1 MHz)
2× ultra-low-power comparators
2× operational amplifiers (8 MHz bandwidth)
1× Digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters
Graphics
LCD-TFT controller supporting up to XGA Resolution
Chrom-ART Accelerator™ graphical hardware accelerator (DMA2D) for enhanced GUI to reduce CPU load
Hardware JPEG Codec
1× high-resolution timer (2.5 ns max resolution)
2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
2× 16-bit advanced motor control timers
10× 16-bit general-purpose timers
5× 16-bit low-power timers
2× watchdogs (independent and window)
1× SysTick timer
RTC with sub-second accuracy and hardware calendar
Debug mode
SWD & JTAG interfaces
4 Kbyte Embedded Trace Buffer
2× true random number generator (3 oscillators each)
96-bit unique ID
All packages are ECOPACK®2 compliant
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Key Features
Core
32-bit ARM® Cortex®-M7 core with double-precision FPU and L1 cache: 16 KB of data and 16 KB of instruction cache allowing to fill one cache line in a single access from the 256-bit embedded Flash memory; frequency up to 400 MHz, MPU, 856 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
Memories
Up to 2 MB of Flash memory with read while write support
~1 MB of RAM: 192 KB of TCM RAM (inc. 64 KB of ITCM RAM + 128 KB of DTCM RAM for time critical routines), 864 KB of user SRAM, and 4 KB of SRAM in Backup domain
Dual mode Quad-SPI memory interface
Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
CRC calculation unit
Security
ROP, PC-ROP, active tamper
Reset and power management
3 separate power domains which can be independently set in low-power mode to maximize power efficiency (clock gated or switched off)
1.62 to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
Voltage scaling in Run and Stop mode
Backup regulator (~0.9 V)
Voltage reference for analog peripheral and VREF+
Low-power modes: Sleep, Stop and Standby
Low-power consumption
Total current consumption down to 7 μA
Clock management
Internal oscillators: 64 MHz HSI oscillator, 48 MHz RC oscillator, 4 MHz CSI oscillator, 40 kHz LSI oscillator
External oscillators: 1-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
3x PLLs (1 for the system clock, 2 for kernel clocks) with fractional mode
General-purpose input/outputs
Up to 168 I/O ports with interrupt capabilityUp to 4 fast I/Os up to 166 MHzUp to 89 I/Os up to 83 MHzUp to 164 5 V-tolerant I/Os
Interconnect matrix
4 DMA controllers to unload the CPU
Up to 35 communication peripherals
4× I2C FM+ interfaces (SMBus/PMBus)
4× USART/4x UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1× LPUART
6× SPIs, including 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock and 1x I2S in LP domain
4× SAIs (serial audio interface)
SPDIFRX interface
SWPMI single-wire protocol master I/F
MDIO Slave interface
2× SD/SDIO/MMC interfaces
2× CAN controllers supporting CAN FD protocol, out of which one supports time-triggered CAN (TT-CAN)
2× USB OTG interfaces (1FS, 1HS/FS)
Ethernet MAC interface with DMA controller
HDMI-CEC
8- to 14-bit camera interface up to 80 MHz
11 analog peripherals
3× ADCs with 16-bit max. resolution (14 bits 2.7 MSPS, 16 bits 168 kSPS)
1× temperature sensor
2× 12-bit D/A converters (1 MHz)
2× ultra-low-power comparators
2× operational amplifiers (8 MHz bandwidth)
1× Digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters
Graphics
LCD-TFT controller supporting up to XGA Resolution
Chrom-ART Accelerator™ graphical hardware accelerator (DMA2D) for enhanced GUI to reduce CPU load
Hardware JPEG Codec
1× high-resolution timer (2.5 ns max resolution)
2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
2× 16-bit advanced motor control timers
10× 16-bit general-purpose timers
5× 16-bit low-power timers
2× watchdogs (independent and window)
1× SysTick timer
RTC with sub-second accuracy and hardware calendar
Debug mode
SWD & JTAG interfaces
4 Kbyte Embedded Trace Buffer
2× true random number generator (3 oscillators each)
96-bit unique ID
All packages are ECOPACK®2 compliant
先看看原理图：https://www.stmcu.org.cn/document/detail/index/id-217977
另外，没看到说的下架啊
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