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STM32F429DISCOVERY板学习控制外部SDRAM例程，下面是官方的库例程和注释，（来自STM32F4CUBE V1.14.0），它注释的时钟周期是11.90ns，应该是1/（168M/2）这样算的，实际上它HCLK=180M,而且SDRAM时钟他配置的是60M，所以周期应该是1/60M=16.67ns才对啊。但是在后边刷新率的计算上确实这样算的，64ms/4096*90M-20=1385（0x569），按它实际的配置应该是64ms/4096*60M-20=918（0x396）才对啊。关于我说的这点，有没有人注意过还是我理解错了？ #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 /* TMRD: 2 Clock cycles */ SDRAM_Timing.LoadToActiveDelay = 2; /* TXSR: min=70ns (6x11.90ns) */ SDRAM_Timing.ExitSelfRefreshDelay = 7; /* TRAS: min=42ns (4x11.90ns) max=120k (ns) */ SDRAM_Timing.SelfRefreshTime = 4; /* TRC: min=63 (6x11.90ns) */ SDRAM_Timing.RowCycleDelay = 7; /* TWR: 2 Clock cycles */ SDRAM_Timing.WriteRecoveryTime = 2; /* TRP: 15ns => 2x11.90ns */ SDRAM_Timing.RPDelay = 2; /* TRCD: 15ns => 2x11.90ns */ SDRAM_Timing.RCDDelay = 2; hsdram.Init.SDBank = FMC_SDRAM_BANK2; hsdram.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; hsdram.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; hsdram.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; hsdram.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; hsdram.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3; hsdram.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; hsdram.Init.SDClockPeriod = SDCLOCK_PERIOD; hsdram.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE; hsdram.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1; #define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90MHz SD clock) */ HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT); static void SystemClock_Config(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; /* Enable Power Control clock */ __HAL_RCC_PWR_CLK_ENABLE(); /* The voltage scaling allows optimizing the power consumption when the device is clocked below the maximum system frequency, to update the voltage scaling value regarding system frequency refer to product datasheet. */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /* Enable HSE Oscillator and activate PLL with HSE as source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = 8; RCC_OscInitStruct.PLL.PLLN = 360; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 7; HAL_RCC_OscConfig(&RCC_OscInitStruct); /* Activate the Over-Drive mode */ HAL_PWREx_EnableOverDrive(); /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); } |
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