NUCLEO-L073RZ LSE时钟不能初始化
试了两块板子，毛病一样。晶振也换了。代码如下LL_RCC_LSE_Enable();//=>RCC->CSR |=RCC_CSR_LSEON;
//卡在此处循环,LSE不起振
while(!LL_RCC_LSE_IsReady())//while(0==(RCC->CSR & RCC_CSR_LSERDY))
{
result=LL_RCC_LSE_IsReady(); //返回值 0
result=LL_RCC_LSE_IsCSSDetected();//返回值 0
}
望大神指教！拜谢! 换LSI试下，如果内部没问题，拿示波器去找硬件问题 LSI是正常的，LSE死活不起振。开始以为是硬件问题，两个板都一个样。而且另一块板还换了一下晶振。接LSE的PC引脚当普通GPIO使用也正常。真是郁闷，搞好几天了。没找到原因。 要不用CubeMX生成一下code 試試看
估计是代码不对，我用HAL可以启动，追了一下HAL库内代码，好像和备份域有关系
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
FlagStatus pwrclkchanged = RESET;
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
{
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
{
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
} 强制改代码，解决。不过原因还要深入研究，望前辈指教！
void StartLSE(void)
{
#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSERDY_Pos))
#define CR_REG_INDEX ((uint8_t)1)
#define CSR_REG_INDEX ((uint8_t)2)
#define CRRCR_REG_INDEX ((uint8_t)3)
#define RCC_FLAG_MASK ((uint8_t)0x1F)
#define __LL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == CSR_REG_INDEX) ? RCC->CSR :RCC->CRRCR)))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0U ) ? 1U : 0U )
#define LL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define LL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define __LL_RCC_LSE_CONFIG(__STATE__) \
do{ \
if ((__STATE__) == RCC_CSR_LSEON) \
{ \
SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
} \
else if ((__STATE__) == RCC_CSR_OFF) \
{ \
CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
} \
else if ((__STATE__) == RCC_CSR_BYPASS) \
{ \
SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
} \
}while(0)
FlagStatus pwrclkchanged = RESET;
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if((READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) == 0U))
{
SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN));
pwrclkchanged = SET;
}
if(LL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
while(LL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
LL_mDelay(100);
//Timeout
}
}
/* Set the new LSE configuration -----------------------------------------*/
//_LL_RCC_LSE_CONFIG(RCC_CSR_LSEON);
SET_BIT(RCC->CSR, RCC_CSR_LSEON);
/* Wait till LSE is ready */
while(__LL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
{
LL_mDelay(5000);
}
/* Wait till LSE is disabled */
// while(__LL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
// {
// LL_mDelay(5000);
// //³¬Ê±´úÂë
// }
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
{
CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN));
}
#undef RCC_FLAG_LSERDY
#undef CR_REG_INDEX
#undef CSR_REG_INDEX
#undef CRRCR_REG_INDEX
#undef RCC_FLAG_MASK
#undef __LL_RCC_GET_FLAG(__FLAG__)
#undef LL_IS_BIT_CLR(REG, BIT)
#undef LL_IS_BIT_SET(REG, BIT)
#undef __LL_RCC_LSE_CONFIG(__STATE__)
}
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