STM32F030锁相环配置与读取不一致
本帖最后由 donsbin 于 2017-8-21 21:36 编辑外挂8M的晶振,锁相环通过HSE一分频然后倍频。
通过RCC_GetClocksFreq(&gRCC_Clocks);接口读取时钟信息。
论坛下的DEMO
通过IAR编译DEBUG读取数据如下,主频变成了13.5M的了
然后我又用MDK DEBUG了下,16M。正常了
static RCC_ClocksTypeDef gRCC_Clocks;
voidBSP_Init (void)
{
//BSP_IntInit();
RCC_DeInit();
RCC_HSEConfig(RCC_HSE_ON); /* HSE = 4MHz --> 32 MHz range */
RCC_WaitForHSEStartUp();
RCC_HCLKConfig(RCC_SYSCLK_Div1); /* HCLK= AHBCLK= PLL / AHBPRES(1) =48MHz.(max) */
RCC_PCLKConfig(RCC_HCLK_Div1);
RCC_PLLConfig(RCC_PLLSource_PREDIV1, /* PCLK = PLL clock must be set from 16MHz --> 48MHz */
(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL2));
RCC_PLLCmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) { /* Wait for PLL to lock. */
/* wait */;
}
FLASH_SetLatency(FLASH_Latency_1); /* 1 Flash wait states */
FLASH_PrefetchBufferCmd(ENABLE);
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* HCLK = SYSCLK = PLL */
while (RCC_GetSYSCLKSource() != RCC_CFGR_SWS_PLL) { /* Check for clock source */
;
}
RCC_GetClocksFreq(&gRCC_Clocks);
BSP_LED_Init(); /* Init LEDs. */
}
是不是我IDE配置问题??:dizzy:
这好像这不是标准库,也不是HAL库啊,眼生。
/*
* - 0x00: HSI used as system clock
* - 0x04: HSE used as system clock
* - 0x08: PLL used as system clock
* - 0x0C: HSI48 used as system clock, applicable only for STM32F072 devices */
if(((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)) == 0x08)
{
return ;
}
/* Enable Prefetch Buffer and set Flash Latency */
FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
/* PLL configuration */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMUL2);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
{
} 标准库也试过了,一模一样
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